S/UNI®-JET Data Sheet
Released
Register 364H: RXCP-50 Status/Interrupt Status
Bit
Type
R
R
Function
OOCDV
LCDV
Unused
OOCDI
CHCSI
UHCSI
FOVRI
LCDI
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
R
R
R
LCDI
The LCDI bit is set high when there is a change in the loss of cell delineation (LCD) state.
This bit is reset immediately after a read to this register.
FOVRI
The FOVRI bit is set to logic one when a FIFO overrun occurs. This bit is reset immediately
after a read to this register. No further FIFO overrun indications will occur until the condition
which caused the original overrun has cleared. In the case where continuous FIFO overruns
are occurring, only a single overrun indication (FOVRI -> ‘1’) will be recorded until the
overruns cease.
UHCSI
The UHCSI bit is set high when an uncorrected HCS error is detected. This bit is reset
immediately after a read to this register.
CHCSI
The CHCSI bit is set high when a corrected HCS error is detected. This bit is reset
immediately after a read to this register.
OOCDI
The OOCDI bit is set high when the RXCP-50 enters or exits the SYNC state. The OOCDV
bit indicates whether the RXCP-50 is in the SYNC state or not. The OOCDI bit is reset
immediately after a read to this register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
199
PMC [ PMC-SIERRA, INC ]
