S/UNI®-JET Data Sheet
Released
Register 362H: RXCP-50 FIFO/UTOPIA Control & Configuration
Bit
Type
R/W
Function
RXPTYP
Unused
RCAINV
RCALEVEL0
Unused
Unused
Unused
FIFORST
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
0
1
X
X
X
0
R/W
R/W
R/W
FIFORST
The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST is set to logic
zero, the FIFO operates normally. When FIFORST is set to logic one, the FIFO is
immediately emptied and further writes into the FIFO are ignored (no incoming ATM cells
will be stored in the FIFO). The FIFO remains empty and continues to ignore writes until a
logic zero is written to FIFORST.
See section 12.8 on resetting the receive and transmit FIFOs.
RCALEVEL0
The RCALEVEL0 register bit selects the behavior of RCA and DRCA[x] when they de-assert
(transition to logic zero if RCAINV is logic zero, or transition to logic one if RCAINV is
logic one) as the receive FIFO empties.
When RCALEVEL0 is set to logic one, DRCA[x] and RCA indicates that the receive FIFO is
empty. RCA (and DRCA[x]), if polled, will de-assert on the rising RFCLK edge after Payload
byte 48 (ATM8=1) or Payload byte 24 (ATM8=0) is output.
When RCALEVEL0 is set to logic zero, DRCA[x] and RCA, if polled, indicates that the
receive FIFO is near empty. DRCA[x] and RCA, if polled, will de-assert on the rising
RFCLK edge after Payload byte 43 (ATM8=1) or Payload byte 19 (ATM8=0) is output.
RCAINV
The RCAINV bit inverts the polarity of the DRCA[x] and RCA output signal. When
RCAINV is a logic one, the polarity of DRCA[x] and RCA is inverted (DRCA[x] and RCA at
logic zero means there is a receive cell available to be read). When RCAINV is a logic zero,
the polarity of RCA and DRCA[x] is not inverted.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
195
PMC [ PMC-SIERRA, INC ]
