S/UNI®-JET Data Sheet
Released
Register 31AH: PMON Parity Error Event Count LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
PERR[7]
PERR[6]
PERR[5]
PERR[4]
PERR[3]
PERR[2]
PERR[1]
PERR[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Register 31BH: PMON Parity Error Event Count MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
PERR[15]
PERR[14]
PERR[13]
PERR[12]
PERR[11]
PERR[10]
PERR[9]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
PERR[8]
PERR[15:0]
PERR[15:0] represents the number of DS3 P-bit errors, the number of E3 G.832 BIP-8 errors
or the number of J2 CRC-5 errors that have been detected since the last time the parity error
counter was polled.
The counter (and all other counters in the PMON) is polled by writing to any of the PMON
register addresses (314H to 31FH) or to the S/UNI-JET Identification, Master Reset, and
Global Monitor Update Register (006H). Such a write transfers the internally accumulated
count to the PERR Error Count Registers and simultaneously resets the internal counter to
begin a new cycle of error accumulation. This transfer and reset is carried out in a manner
that coincident events are not lost. The transfer takes 255 RCLK cycles to complete in DS3
mode and three RCLK cycles to complete in E3 and J2 mode.
This counter is paused when the corresponding framer has lost frame alignment.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
119
PMC [ PMC-SIERRA, INC ]
