S/UNI®-JET Data Sheet
Released
Register 311H: PMON Interrupt Enable/Status
Bit
Type
Function
Unused
Unused
Unused
Unused
Unused
INTE
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
0
R/W
R
R
INTR
OVR
X
X
OVR
The OVR bit indicates the overrun status of the PMON holding registers. A logic one in this
bit position indicates that a previous interrupt has not been cleared before the end of the next
accumulation interval, and that the contents of the holding registers have been overwritten. A
logic zero indicates that no overrun has occurred. This bit is reset to logic zero when this
register is read.
INTR
The INTR bit indicates the current status of the interrupt signal. A logic one in this bit
position indicates that a transfer of counter values to the holding registers has occurred; a
logic zero indicates that no transfer has occurred. The INTR bit is set to logic zero when this
register is read.
INTE
The INTE bit enables the generation of an interrupt when the PMON counter values are
transferred to the holding registers. When a logic one is written to INTE, the interrupt
generation is enabled.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
115
PMC [ PMC-SIERRA, INC ]
