S/UNI®-JET Data Sheet
Released
Register 318H: PMON Excessive Zero Count LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
EXZS[7]
EXZS[6]
EXZS[5]
EXZS[4]
EXZS[3]
EXZS[2]
EXZS[1]
EXZS[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Register 319H: PMON Excessive Zero Count MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
EXZS[15]
EXZS[14]
EXZS[13]
EXZS[12]
EXZS[11]
EXZS[10]
EXZS[9]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
EXZS[8]
EXZS[15:0]
In DS3 mode, EXZS[15:0] represents the number of summed Excessive Zeros (EXZS) that
occurred during the previous accumulation interval. One or more excessive zeros occurrences
within an 85 bit DS3 information block is counted as one summed excessive zero. Excessive
zeros are accumulated by this register only when the EXZSO and EXZDET are logic one in
the DS3 FRMR Additional Configuration Register. This register accumulates summed LCV
when the EXZSO is logic zero. The count of summed LCV is defined as the number of DS3
information blocks (85 bits) that contain one or more LCV since the last time the summed
LCV counter was polled.
The counter (and all other counters in the PMON) is polled by writing to any of the PMON
register addresses (314H to 31FH) or to the S/UNI-JET Identification, Master Reset, and
Global Monitor Update Register (006H). Such a write transfers the internally accumulated
count to the EXZS Event Count Registers and simultaneously resets the internal counter to
begin a new cycle of error accumulation. This transfer and reset is carried out in a manner
that coincident events are not lost. The transfer takes 255 RCLK cycles to complete in DS3
mode and a maximum of 500 RCLK cycles to complete in G.832 E3 mode.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
118
PMC [ PMC-SIERRA, INC ]
