S/UNI®-JET Data Sheet
Released
Register 316H: PMON Framing Bit Error Event Count LSB
Bit
Type
R
R
R
R
R
R
R
R
Function
FERR[7]
FERR[6]
FERR[5]
FERR[4]
FERR[3]
FERR[2]
FERR[1]
FERR[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
317H: PMON Framing Bit Error Event Count MSB
Bit
Type
Function
Unused
Unused
Unused
Unused
Unused
Unused
FERR[9]
FERR[8]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
FERR[9:0]
FERR[9:0] represents the number of DS3 F-bit and M-bit errors, or E3 or J2 framing pattern
errors, that have been detected since the last time the framing error counter was polled.
The counter (and all other counters in the PMON) is polled by writing to any of the PMON
register addresses (314H to 31FH) or to the S/UNI-JET Identification, Master Reset, and
Global Monitor Update Register (006H). Such a write transfers the internally accumulated
count to the FERR Error Event Count Registers and simultaneously resets the internal counter
to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner
that coincident events are not lost. The transfer takes 255 RCLK cycles to complete in DS3
mode and three RCLK cycles to complete in E3 and J2 mode.
This counter is paused when the corresponding framer has lost frame alignment.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
117
PMC [ PMC-SIERRA, INC ]
