PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Figure 43
- Microprocessor Interface Write Timing
A[10:1]
Valid Address
tS
tH
ALW
ALW
tV
tS
tH
LW
L
LW
ALE
(CSB+WRB)
D[15:0]
tS
tV
tS
tH
AW
AW
WR
tH
DW
DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2. In non-multiplexed address/data bus architectures, ALE should be held high so that
parameters tSALW, tSALW, tVL, tSLW and tHLW are not applicable.
3. Parameter tHAW is not applicable if address latching is used.
Table 42
RTSB Timing
Description
Symbol
Min
Max
Units
tVRSTB
RSTB Pulse
Width
100
Ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
306
PMC [ PMC-SIERRA, INC ]
