PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Symbol
Parameter
Min
Max
Units
Valid Read Negated to Output
Tristate
50
ns
tZINTH
Figure 42
- Microprocessor Interface Read Timing
tS
AR
A[10:1]
Valid
Address
tH
AR
tS
ALR
tV
tH
L
ALR
ALE
tH
tS
LR
LR
(CSB+RDB)
tZ
INTH
INTB
tZ
tP
RD
RD
D[15:0]
Valid Data
Notes on Microprocessor Interface Read Timing:
1. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus (D[15:0]).
2. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
304
PMC [ PMC-SIERRA, INC ]
