PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x078: LCD Count Threshold
Bit
Type
Function
Default
15:8
7:0
Unused
LCDC[7:0]
R/W
0x68
LCDC[7:0]:
The LCDC[7:0] bits represent the number of consecutive cell periods the
receive cell processor must be out of cell delineation before loss of cell
delineation (LCD) is declared. Likewise, LCD is not deasserted until the
receive cell processor is in cell delineation for the number of cell periods
specified by LCDC[7:0].
The default value of LCDC[7:0] is 104; this translates to 28 ms at 1.5 Mbps.
11.6 Line Clock/Data Interface
Register 0x100: RCAS Indirect Link and Time-slot Select
Bit
Type
Function
Default
15
14
13:11
10:8
7:5
R
BUSY
RWB
Unused
LINK[2:0]
Unused
TSLOT[4:0]
X
0
0
0
X
00
R/W
R/W
R/W
4:0
R/W
This register provides the link number and time-slot number used to access the time-
slot provision RAM. Writing to this register triggers an indirect register access.
TSLOT[4:0]:
The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be
configured or interrogated in the indirect access. For a channelized T1 link,
time-slots 1 to 24 are valid. For a channelized E1 link, time-slots 1 to 31 are
valid. For unchannelized links, only time-slot 0 is valid.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
135
PMC [ PMC-SIERRA, INC ]
