PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
LINK[2:0]:
The indirect link number bits (LINK[2:0]) select amongst the 8 receive links to
be configured or interrogated in the indirect access.
RWB:
The indirect access control bit (RWB) selects between a configure (write) or
interrogate (read) access to the timeslot provision RAM. The address to the
timeslot provision RAM is constructed by concatenating the TSLOT[4:0] and
LINK[2:0] bits. Writing a logic zero to RWB triggers an indirect write operation.
Data to be written is taken from the PROV, the VLDLBEN, and the VLINK[2:0]
bits of the Indirect Link Data register. Writing a logic one to RWB triggers an
indirect read operation. Addressing of the RAM is the same as in an indirect
write operation. The data read can be found in the PROV, the VLDLBEN, and
the VLINK[2:0] bits of the Indirect Link Data register.
BUSY:
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when this register is written; this is done to trigger
an indirect access, and will stay high until the access is complete. At which
point, BUSY will be set low. This register should be polled to determine either:
(1) when data from an indirect read operation is available in the Indirect Data
register or (2) when a new indirect write operation may commence.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
136
PMC [ PMC-SIERRA, INC ]
