S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
10.4 VC Record Table...............................................................................................80
10.5 Cell Processing .................................................................................................80
10.6 Header Translation............................................................................................90
10.7 Cell Rate Policing..............................................................................................91
10.7.1 Per-VC Policing....................................................................................91
10.7.2 Per-PHY Policing..................................................................................98
10.7.3 Guaranteed Frame Rate Policing.......................................................101
10.8 Cell Counting...................................................................................................103
10.9 Operations, Administration and Maintenance (OAM) Cell Servicing ..............104
10.9.1 Fault Management Cells ....................................................................105
10.9.2 Loopback Cells...................................................................................107
10.9.3 Activation/Deactivation Cells..............................................................107
10.9.4 System Management Cells ................................................................107
10.9.5 Automated Protection Switching Cells ...............................................108
10.9.6 Resource Management Cells.............................................................108
10.10 F4 to F5 OAM Processing...............................................................................108
10.11 F5 to F4 OAM Processing...............................................................................116
10.12 Constraints on F5 and F4 VC Table Record Addresses .................................116
10.13 Background Processes...................................................................................117
10.14 Performance Management .............................................................................118
10.14.1 Performance Management Flows ......................................................118
10.14.2 Performance Management Record Table ..........................................121
10.15 Change of Connection State FIFO..................................................................129
10.16 Count Rollover FIFO .......................................................................................130
10.17 Cell Routing.....................................................................................................133
10.17.1 Output Backward OAM Cell Interface ................................................134
10.17.2 Input Backward OAM Cell Interface...................................................138
10.17.3 Internal DRAM Access .......................................................................139
10.17.4 Writing Cells .......................................................................................140
10.17.5 Reading Cells.....................................................................................141
10.18 JTAG Test Access Port....................................................................................143
11 Normal Mode Register Description...........................................................................144
11.1 List of Registers ..............................................................................................144
11.2 Core Registers ................................................................................................151
11.3 Microprocessor Cell Interface .........................................................................169
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
9
PMC [ PMC-SIERRA, INC ]
