S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Issue
No.
2
Issue Date
Details of Change
Feb 2000
Core logic changed to 1.5V. VC Table parity replaced with CRC-10. “Bwd PM
Pending” bit extended for use with Fwd PM Permission cells. VPRMSEL
replaced with the more descriptive VP_RM_PTI6. Search key diagrams
corrected of typos. Added 1 reserved bit to Source field of Count Rollover
FIFO. Fixed TPU_ADDR signal in Figure 6. Fixed PM RAM access
ClearOnRd defaults. Removed DMA Request Enable. Moved DMAREQINV
to the MCIF. Renamed all references to DMA REQ correctly. Added
UPURS_to_OCIF. Added 1 bit to Cell Type field of UPURS and BCIF
causation words to add many more cell types. Deleted 1 bit from source ID of
the BCIF causation word to make room. Changed all references to AUTOAIS
to AUTO_AIS to ensure consistency. Added APStoBCIF and ActDeToBCIF
bits. InactivetoUP applies to connections disabled due to CRC errors. Bwd LB
cells are not routed to the micro at flow end-points unless the source ID
matches the programmed Loopback Location ID, unless the
Bwd_LB_to_UP_at_End bit is logic 1. XCLK added to Clock Activity monitor.
Device now powers-up in reset, must be held there to allow the DRAM to
settle for 200 us. Per-PHY counting bit descriptions of Cnt_Inv_OAM and
Cnt_Rsvd_VCI_PTI corrected. Added VPC Counting. Added Policing Rollover
FIFO Enable bits. Added FREE[7:0]. Added LBtoOCIF. Added
RxPHYTxPHY internal test bit. Made Maximum Frame Length test disabled if
MFL = all ones, to match ATLAS. Added feature for allowing CC alarms to not
generate COS entries, via the OAM Config status bit. Added a globally
enabled feature that permits Bwd PM cells to carry the Fwd PM Cell’s time
stamp, if the Bwd PM cell is able to be generated immediately. Added Don’t-
Touch designation for OC-48C cascading. SDQ register map substantially
reorganized. Meanings of Buffer Available and Data Available thresholds
changed slightly. SDQ per-PHY counts reduced to 4 bits; aggregate cell count
increased to 32 bits. Added generic names for UL3/PL3 pins for easier
reference. INBANDADDR function added to PL3 blocks to accommodate
single-PHY operation. Updated SRAM configuration diagrams and
descriptions to reflect xclk/sclk_o/sysclk scheme. Updated SRAM AC and
Functional timing to illustrate relationship of SCLK_O, SYSCLK. Reduced VC
depth to 64K VCs from 128K VCs. Updated PL3 pin descriptions to match
latest POS-PHY release (release 4). Added PL3/UL3 AC timing. Clarified the
meaning of “noting” non-compliant cells in policing by saying “just counted”.
Documented fact that packet counting is based on CLP of EOM. Updated
references to other documents (ATLAS, UL3, I.610). Corrected formatting of
COS FIFO, and simplified the bit description. Corrected the reset value of
Per-PHY Processing Enable Register 2.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
5
PMC [ PMC-SIERRA, INC ]
