S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Issue
No.
3
Issue Date
Details of Change
Oct 2000
Clarified that UPURS_to_OCIF overrides XPREPO, and that PROC_CELL or
PROCESS_PHY overrides XPREPO. Absolute Maximum ratings updated
(SRAM interface specced relative to VDD25; absolute min voltage changed to
–0.3, absolute max to VDDx+0.3, Max current on pins reduced to 10mA).
Clarified translation options to BCIF. Added Mkt_NUM register in ID register.
Added dropped-cells counter on MCIF. Added note that reserved fields in the
Search and Linkage tables must be programmed to logic 0 for proper
operation. Adjusted format of Count Rollover FIFO. Added extra notes about
the restriction on the 2 LSBs of the VPC Pointer. Changed Inact_on_Par_Err
to Inact_on_DRAM_Err. Corrected RxL, TxL Indirect Address register.
Increased min prop delay on UL3/PL3 to 1.5 ns. Changed package from 576
to 768 TBGA. Split SCLK_O into SYSCLK_O and SRAMCLK_O. Added
Timeout_To_UP bit to Register 0x100. Renamed AIS_VPC to Sending_AIS.
Changed COS fifo description to show all bits. Renamed a few of the CP
interrupts to have more expressive names. Clarified that Returned LB cells are
translated like other generated cells (RDI and Bwd PM). Renamed F4toF5AIS
to F4toF5OAM to reflect the fact it controls both AIS and RDI. Clarified the
difference between Block_Ptr and FIFO_Number in the SDQ Configuration
description. Clarified that Ete Loopback cells are looped back at end-to-end
points if their LLID = all 1, or if it matches the LLID of the end point. Modified
Sat_PM_BIP16 to Sat_Fast_PM_Counts and made it affect the Lost PM Cell
Counts as well. Changed drop_vc to have no effect on the generation of OAM
cells to the BCIF. F5 AIS cells due to F4 AIS carry the F4 AIS defect
location/type. When F4-to-F5, per-PHY or CC AIS is generated, then if
ATLAS is within a segment for that VC, both Segment and ETE AIS are
generated. Changed “SCSB” to “SCEB” for consistency. Fixed an
inconsistency in fm_interrupt_enable naming. Corrected description of EFCI
count. Updated PM documentation to better reflect behavior with SECBs.
Added documentation that Count Rollover for lost PM cell counts can be
suppressed. Corrected definition of reserved vpi/vci. Clarified allowable
settings of Action 1 and Action 2 in GFR policing. Note added that 2.5V I/Os
are not 3.3V tolerant. SDQ register map and configuration dramatically
simplified: eliminated FIFO numbers, buffer thresholds become fixed, banks
eliminated, block size increased, starting point restrictions removed, interrupts
reorganized. SDQ per-PHY cell counter measures fill level rather than
throughput. Updated the TxLink documentation. Produced much more
precise definitions of PTPA and STPA on both input and output. Bwd VCRA
moved from Linkage row to VC Table Row 0. Added BCIF AC timing. RDB
low to microprocessor data valid propagation delay increased to 30 ns. RDB
high to microprocessor data tristate extended to 13 ns. WRB high to
Microprocessor Data hold time extended to 3 ns. SRAMCLK_O to SRAM
output data and control valid extended from 4.5 to 5.5 ns (SRAM setup is 1.5
ns, allowing 1 ns slack). Added minimum XCLK frequency. Power tolerances
set to 0.3V on 3.3V power, 0.2V on 2.5V power, 0.075 on 1.5V power. Added
per-VP policing.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
6
PMC [ PMC-SIERRA, INC ]
