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PM7325-TC 参数 Datasheet PDF下载

PM7325-TC图片预览
型号: PM7325-TC
PDF下载: 下载PDF文件 查看货源
内容描述: S / UNI - ATLAS -3200电信标准产品数据表初步 [S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet Preliminary]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信电路异步传输模式
文件页数/大小: 432 页 / 2222 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet  
Preliminary  
11.4 Backward Cell Interface..................................................................................176  
11.5 Cell Processor.................................................................................................190  
11.5.1 General Configuration and Status......................................................190  
11.5.2 Search................................................................................................219  
11.5.3 VC Table.............................................................................................225  
11.5.4 Policing...............................................................................................242  
11.5.5 OAM Fault Management....................................................................259  
11.5.6 OAM Loopback...................................................................................270  
11.5.7 OAM Performance Management .......................................................272  
11.5.8 Change of Connection State FIFO.....................................................286  
11.5.9 Count Rollover FIFO ..........................................................................288  
11.5.10 Per PHY Statistics ..............................................................................291  
11.6 Rx Link Interface .............................................................................................308  
11.7 Tx PHY Interface.............................................................................................318  
11.8 Input Scalable Data Queue.............................................................................323  
11.9 Rx PHY Interface ............................................................................................334  
11.10 Tx Link Interface .............................................................................................344  
11.11 Output Scalable Data Queue..........................................................................354  
11.12 Packet Bypass Scalable Data Queue.............................................................365  
12 Test Features Description .........................................................................................376  
12.1 Test Mode 0 Details.........................................................................................378  
12.2 JTAG Test Port................................................................................................379  
13 Operations.................................................................................................................390  
13.1 Configuring the Scalable Data Queue ............................................................390  
13.2 JTAG Support..................................................................................................392  
13.2.1 TAP Controller ....................................................................................394  
13.3 Board Design Recommendations ...................................................................396  
14 Functional Timing......................................................................................................397  
14.1 POS-PHY Level 3 ...........................................................................................397  
14.1.1 Ingress Packet Interface ....................................................................397  
14.1.2 Egress Packet Interface.....................................................................403  
14.2 UTOPIA Level 3 ..............................................................................................408  
14.2.1 Ingress UL3 Interface.........................................................................409  
14.2.2 Egress UL3 Interface .........................................................................412  
14.3 SRAM Interface...............................................................................................415  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-1990553, Issue 4  
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