S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
List of Registers
Register 0x000: S/UNI-ATLAS-3200 Master Configuration And Reset .........................151
Register 0x001: S/UNI-ATLAS-3200 Identity / Load Counts..........................................154
Register 0x002: Master Interrupt Status #1 ...................................................................156
Register 0x003: Master Interrupt Status #2 ...................................................................162
Register 0x004: Master Interrupt Enable #1 ..................................................................164
Register 0x005: Master Interrupt Enable #2 ..................................................................166
Register 0x006: Master Clock Monitor ...........................................................................167
Register 0x020: Microprocessor Cell Interface Control and Status ...............................169
Register 0x021: Microprocessor Cell Data.....................................................................173
Register 0x022: MCIF Dropped Cells Counter...............................................................175
Register 0x030: Input Backwards Cell Interface Configuration......................................176
Register 0x031: IBCIF Dropped Cells Counter ..............................................................178
Register 0x032: IBCIF Read Cells Counter ...................................................................179
Register 0x038: Output Backwards Cell Interface Configuration...................................180
Register 0x039: OBCIF Dropped Cells Counter ............................................................181
Register 0x03A: OBCIF Read Cells Counter .................................................................182
Register 0x040: SYSCLK Delay Locked Loop Register 1..............................................183
Register 0x041: SYSCLK DLL Register 2......................................................................185
Register 0x042: SYSCLK DLL Register 3......................................................................186
Register 0x043: SYSCLK DLL Register 4......................................................................187
Register 0x100: Cell Processor Configuration ...............................................................190
Register 0x101: Cell Processor Routing Configuration..................................................197
Register 0x102: Cell Counting Configuration.................................................................203
Register 0x104: Backward Cell Interface Pacing and Head of Line Blocking................205
Register 0x105: Per-PHY Processing Enable 1.............................................................207
Register 0x106: Per-PHY Processing Enable 2.............................................................209
Register 0x107: AIS/CC Pacing and Head of Line Blocking..........................................211
Register 0x108: Fwd PM Pacing and Head of Line Blocking.........................................213
Register 0x109: Inoperative PHY Declaration Period and Indications...........................215
Register 0x10A: Inoperative PHY Indications ................................................................217
Register 0x10B: Search Engine Configuration...............................................................219
Register 0x10C: SRAM Access Control.........................................................................221
Register 0x10D: SRAM Data LSW (SRAM Data[31:0]) .................................................223
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
12
PMC [ PMC-SIERRA, INC ]
