S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Bit
3
Name
VC_to_UP
Description
If this bit is logic 1, all cells arriving on this connection are copied,
unaltered except for the insertion of the Cell Info Field, to the
Microprocessor Cell Interface
2
Drop_VC
If this bit is a logic 1, no cells are routed to the OCIF. The setting of
this bit supercedes all other routing bits. If the Drop_VC bit is set,
the S/UNI-ATLAS-3200 will not output generated OAM cells to the
OCIF (AIS, CC, Fwd PM). Drop_VC has no effect on the generation
of OAM cells to the BCIF. If Drop_VC = 1 and VC_to_BCIF = 1,
then it is assumed that a per-VC loopback function is being
implemented, and cells from the IBCIF will be permitted to proceed
to the OCIF, and will not be sent to OBCIF. All other cells will be
sent to OBCIF, and not sent to OCIF.
1
0
Rollover_FIFO_enable
COS_FIFO_enable
Enables the 32-bit billing counts to generate entries in the Count
Rollover FIFO whenever their MSB becomes logic 1. If the Count
Rollover FIFO is full, the MSB will remain logic 1 until an entry has
been successfully generated, at which time the MSB will become
logic 0. If this bit is logic 0, then the counts operate as normal
saturating counters, and must be polled periodically by the
microprocessor.
Enables changes in the Status field to result in COS FIFO entries.
Table 12 Internal Status VC Table Field
Bit
Name
Description
20
19
18
Reserved
Reserved
Sending_AIS
This bit must be programmed to logic 0 for backwards compatibility.
This bit must be programmed to logic 0 for backwards compatibility.
If this bit is logic 1, this connection transmitted an AIS cell at the last
one-second processing interval. This indicates that, if a half-second
background process is being executed, the cause of AIS is not new,
and no AIS should be sent until the next one-second process.
This bit should be set to logic 0 when the connection is set up.
17
Sending_RDI_Seg
This bit enables the S/UNI-ATLAS-3200 to generate the first
segment RDI cell within 500msec of detecting a condition which
requires the generation of segment RDI cells.
This bit is set to logic 1 by the S/UNI-ATLAS-3200 when a segment
RDI cell is transmitted, and set to logic 0 when the RDI background
process determines there is no reason to continue sending segment
RDI. In addition to setting this bit when transmitting a segment RDI
cell on reception of an AIS cell, the S/UNI-ATLAS-3200 will use the
0.5 second background process to scan through all connections and
determine if a segment RDI cell is to be transmitted (within 0.5
seconds of detecting the appropriate condition). When the first
segment RDI cell is transmitted, this bit is asserted and subsequent
segment RDI cells are only transmitted by the 1 second background
process.
If this bit is logic 0, the S/UNI-ATLAS-3200 has not yet begun to
transmit segment RDI cells (possibly due the RDI BCIF being full).
This bit should be set to logic 0 when the connection is set up.
16
Sending_RDI_Ete
This bit enables the S/UNI-ATLAS-3200 to generate the first end-to-
end RDI cell within 500msec of detecting a condition which requires
the generation of end-to-end RDI cells.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
84
PMC [ PMC-SIERRA, INC ]
