S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Bit
Name
Description
when it is read in the subsequent second, the RDI_segment Alarm
is cleared.
This field should be set to 0 when the connection is set up.
5:4
End_RDI_Count[1:0]
The End_RDI_Count is set to a value of 2 (to provide a 2.5 +/- 0.5
sec count) upon receipt of an end-to-end RDI cell, and decrements
at one second intervals. If the End_RDI_count reaches 0 and is still
0 when it is read in the subsequent second, the RDI_end_to_end
Alarm is cleared.
This field should be set to 0 when the connection is set up.
3:2
1:0
Seg_AIS_Count[1:0]
End_AIS_Count[1:0]
The Seg_AIS_Count is set to a value of 2 (to provide a 2.5 +/- 0.5
sec count) upon receipt of a segment AIS cell, and decrements at
one second intervals. If the Seg_AIS_Count reaches 0 and is still 0
when it is read in the subsequent second, the AIS_segment Alarm is
cleared.
This field should be set to 0 when the connection is set up.
The End_AIS_Count is set to a value of 2 (to provide a 2.5 +/- 0.5
sec count) upon receipt of an end-to-end AIS cell, and decrements
at one second intervals. If the End_AIS_Count reaches 0 and is still
0 when it is read in the subsequent second, the AIS_end_to_end
Alarm is cleared.
This field should be set to 0 when the connection is set up.
Table 13 OAM Configuration VC Table Field
Bit
22
Name
Reserved
Description
This bit must be programmed to logic 0 for backwards compatibility.
21
COS_CC_DIS
When this bit is logic 1, then entering or exiting CC Alarm will not generate
a COS entry. When this bit is logic 0, COS entries are generated as
normal. This feature is intended for use with older equipment that does not
correctly support CC, in order to avoid flooding the microprocessor with
CC-related COS entries.
20
19
18
17
16
Send_AIS_segment
Send_AIS_end_to_end
Send_RDI_segment
Send_RDI_end_to_end
CC_Activate_Segment
If this bit is a logic 1, a segment AIS cell is generated once per second
(nominally).
If this bit is a logic 1, an end-to-end AIS cell is generated once per second
(nominally).
If this bit is a logic 1, a segment RDI cell is generated once per second
(nominally).
If this bit is a logic 1, an end-to-end RDI cell is generated once per second
(nominally).
Enables Continuity Checking on segment flows. If the ForceCC register bit
is logic 0, then when no user or CC cells are transmitted over a 1.0 second
(nominal) interval, a segment CC OAM cell is generated. The segment CC
cell is generated at an interval of one per second (nominally). If the
connection is an F4 OAM connection that is being aggregated, then any
cells transmitted on any of the constituent F5 connections are considered
user cells.
If the ForceCC register bit is logic 1, then when the CC_Activate_Segment
bit is logic 1, a segment CC cell will be generated at an interval of once per
second (nominally), regardless of the flow of user cells. ITU-T I.610
9.2.1.1.2, 9.2.2.1.2.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
86
PMC [ PMC-SIERRA, INC ]
