S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
The VPI/VCI search results in a VCRA[15:0] value which points to a VC Table record. The
fields of each VC Table record are described below.
When a new VC is provisioned, the management software must initialize the contents of the VC
Table record. Once provisioned, the management software can retrieve the contents of the VC
Table record.
Table 9 VC Table Fields used in Cell Processing
Row
0
127
Action 2
(2)
0
2
Inc 2
(14)
Limit 2
(14)
Action 1
(2)
Inc 1
(14)
Limit 1
(14)
Field B
(12)
VPI
VCI
(16)
Bwds VCRA VC Table
(12)
(16)
CRC-10 (10)
Status
(10)
Configuration OAM
(14)
Internal
Policing
Reserved Maximum
GFR State
Policing
ETE Received Segment
1
Configuration Status
Configuration (16)
(11)
Frame Length (3)
Reserved
(3)
Defect Type
(8)
Received
Defect Type
(8)
(23)
(21)
(11)
Alternate Count 2 (32)
Alternate Count 1 (32)
Count 2 (32)
Count 1 (32)
2
3
Unused Remaining Frame Count Non-Compliant Count 3 Non-Compliant Count 2 Non-Compliant Count 1 TAT2 (34)
(1) (11) (16) (16) (16)
TAT1 (34)
Unused Translated VPI (12)
(4)
Translated VCI (16) Translated HEC (8) Translated UDF (24)
Translated Pre/Po 1
(32)
Translated Pre/Po 2
(32)
4
Segment Received Defect Location (128)
5
6
End-to-End Received Defect Location (128)
Table 10 Status VC Table Field
Bit
9
Name
FIFO Must Write
Description
This bit should be set to zero when the connection is setup.
8
DRAM_CRC_Err
When this bit is logic 1, this VC table entry has suffered a DRAM CRC-
10 error. If the Inact_on_DRAM_Error register bit in the Cell Processor
Configuration Register is logic 1, and this bit is a logic 1, then the
connection is considered inactive. This bit can only be cleared by a
microprocessor write.
7
6
OAM_Failure
This bit becomes a logic 1 if a segment or end-to-end RDI, AIS or CC
condition has persisted for 3.5 0.5 seconds. OAM_Failure is cleared
as soon as no RDI, AIS or CC condition remains.
This bit becomes a logic 1 upon receipt of a single end-to-end AIS cell.
The alarm status is cleared upon the receipt of a single user cell or end-
to-end CC cell, or if no end-to-end AIS cell has been received within the
last 2.5 0.5 sec.
AIS_end_to_end alarm
5
AIS_segment alarm
This bit becomes a logic 1 upon receipt of a single segment AIS cell.
The alarm status is cleared upon the receipt of a single user cell or
segment CC cell, or if no segment AIS cell has been received within the
last 2.5 0.5 sec.
4
3
2
RDI_end_to_end alarm
RDI_segment alarm
CC_end_to_end alarm
This bit becomes a logic 1 upon receipt of a single end-to-end RDI cell.
This bit is cleared if no end-to-end RDI cell has been received within the
last 2.5 0.5 sec.
This bit becomes a logic 1 upon receipt of a single segment RDI cell.
This bit is cleared if no segment RDI cell has been received within the
latest 2.5 0.5 sec.
This bit becomes a logic 1 if no user cell or end-to-end CC cell has
been received within the last 3.5 0.5 sec. This bit is cleared upon
receipt of a user cell, or end-to-end CC cell. If this connection is an
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
81
PMC [ PMC-SIERRA, INC ]
