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PM7325-TC 参数 Datasheet PDF下载

PM7325-TC图片预览
型号: PM7325-TC
PDF下载: 下载PDF文件 查看货源
内容描述: S / UNI - ATLAS -3200电信标准产品数据表初步 [S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet Preliminary]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信电路异步传输模式
文件页数/大小: 432 页 / 2222 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet  
Preliminary  
RMtoUP  
If the RMtoUP bit is logic 1, all RM cells are copied to the Microprocessor Cell Interface.  
RM cells are identified PTI=110 for VC-RM cells and by VCI=6 for VP-RM cells. If the  
VP_RM_PTI6 register bit is logic 1, VP-RM cells are further qualified by PTI=110.  
RMtoBCIF  
If the RMtoBCIF bit is logic 1, all RM cells are copied to the Backwards Cell Interface. RM  
cells are identified PTI=110 for VC-RM cells and by VCI=6 for VP-RM cells. If the  
VP_RM_PTI6 register is logic 1, VP-RM cells are further qualified by PTI=110.  
DropRM  
If the DropRM bit is logic 1, all RM cells are dropped (i.e. not passed to the OCIF) though  
they may be passed to the MCIF or BCIF based on the RMtoBCIF and RMtoUP register bits.  
RM cells are identified PTI=110 for VC-RM cells and by VCI=6 for VP-RM cells. If the  
VP_RM_PTI6 register bit of the Search Engine Configuration configuration register is logic  
1, VP-RM cells are further qualified by PTI=110.  
DROPCRCERM  
If this bit is logic 1, all Forward and Backward RM cells with an incorrect CRC-10 are  
discarded. If this bit is logic 0, then all Forward and Backward RM cells are output to the  
Output Cell Interface regardless of whether their CRC-10 is correct or not.  
BADVCtoUP  
If the BADVCtoUP bit is logic 1, all cells with an unprovisioned VPI/VCI are dropped and  
routed to the Microprocessor Cell Interface. If this bit is logic 0, those cells are discarded by  
the S/UNI-ATLAS-3200 without being routed to the Microprocessor Cell Interface.  
DROPINVPTIVCI  
If this bit is logic 1, all F5 (VCC) cells with PTI=111 and all F4 (VPC) cells with a VCI of 7  
through 15 are not routed to the Output Cell Interface. If DROPINVPTIVCI is logic 0, these  
cells are passed transparently.  
INVPTIVCItoUP  
If the INVPTIVCItoUP bit is logic 1, all F5 (VCC) cells with an invalid PTI field (PTI=111)  
and all F4 (VPC) cells with an invalid VCI field (VCI 7 through 15) are copied to the  
Microprocessor Cell Interface. The DROPINVPTIVCI register bit determines whether cells  
with invalid PTI or VCI fields are passed to the Output Cell Interface.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-1990553, Issue 4  
198  
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