S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
F4SAISF5EAIS
The F4SAISF5EAIS register bit controls the generation of F5 end-to-end AIS cells upon the
reception of an F4 segment AIS cell. If this bit is logic 1, an end-to-end VC-AIS cell will be
generated when a segment VPC-AIS cell is terminated at a VPC segment end-point. If this
bit is logic 0, an end-to-end AIS cell will not be generated in this circumstance.
GEN_HALFSECCLK
The GEN_HALFSECCLK bit determines the trigger for processing that relies on background
processing, such as AIS, RDI and CC cell generation. If the GEN_HALFSECCLK is a logic
1, the 0.5 second clock is derived from SYSCLK, which is assumed to be 125 MHz. If
GEN_HALFSECCLK is a logic 0, processing is initiated on the rising edge of the
HALFSECCLK input.
Copy_FwPM_Timestamp
When the Copy_FwPM_Timestamp bit is logic 1, then when a Bwd PM cell is generated to
the BCIF immediately upon reception of a Fwd PM cell (i.e. the BCIF is not full when the
Fwd PM cell arrives) then the timestamp of the generated Bwd PM cell is set equal to the
timestamp of the Fwd PM cell. If the BCIF is full when the Fwd PM cell arrives, or if this bit
is logic 0, then the timestamp of the Bwd PM cell is set to the default all-ones.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
196
PMC [ PMC-SIERRA, INC ]
