S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
AUTO_AIS
The AUTO_AIS bit enables the generation of segment or end-to-end AIS cells while in a
Continuity alarm state. If AUTO_AIS is logic 1, an Ete AIS cell is transmitted once per
second if no user or CC cells have been received in the last 3.5 +/- 0.5 seconds. Segment AIS
cells will also be generated if the SegmentFlow bit for the connection is logic 1. Automatic
AIS generation is enableable on a per-VC basis via the CC_AIS_RDI bit. AIS cells can also
be transmitted if the Send_AIS_segment and Send_AIS_end_to_end bits in the VC Table are
set.
ForceCC
The ForceCC bit controls whether or not the insertion of CC cells is dependent on the user
cell traffic. If ForceCC is logic 0, CC cells are only generated if the CC_Activate_Segment
or CC_Activate_End_to_End per-connection bits are logic 1 and if no user cells have been
transmitted within one second (nominal). If ForceCC is logic 1, CC cells are generated at a
rate of once per second (nominal) if the CC_Activate_Segment or CC_Activate_End_to_End
bits are logic 1.
F4EAISF5SRDI
The F4EAISF5SRDI register bit controls the generation of F5 Segment RDI cells upon the
reception of an F4 End-to-End AIS cell. When this bit is logic 1, a segment VC-RDI cell will
be generated when an end-to-end VPC-AIS cell is terminated at a VPC end-to-end point and
an associated VCC segment end-point is switched from that VPC. If this bit is logic 0, a
segment VC-RDI cell will not be generated in this circumstance.
F4EAISF5EAIS
The F4EAISF5EAIS register bit controls the generation of F5 End-to-End AIS cells upon the
reception of an F4 End-to-End AIS cell. When this bit is logic 1, an end-to-end VC-AIS cell
will be generated when an end-to-end VPC-AIS cell is terminated at a VPC end-to-end point,
and an associated VCC segment end-point is switched from that VPC. If this bit is logic 0, an
end-to-end VC-AIS cell will not be generated in this circumstance.
F4SAISF5ERDI
The F4SAISF5ERDI register bit controls the generation of F5 end-to-end RDI cells upon the
reception of an F4 segment AIS cell. If this bit is logic 1, an end-to-end VC-RDI cell will be
generated when a segment VPC-AIS cell is terminated at a VPC segment end-point, and the
VCC is also an end-to-end point. If this bit is logic 0, an end-to-end VC-RDI cell will not be
generated in this circumstance.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
195
PMC [ PMC-SIERRA, INC ]
