S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
COS_EN
The Change of State FIFO enable (COS_EN) bit enables the monitoring of changes in
connection state. If COS_EN is logic 1, all connections which undergo changes in state (i.e.
AIS, RDI or CC alarm states) can be logged in a Change of State FIFO. This FIFO is 256
entries deep and holds a copy of the per-connection Status field of the VC Table. Using this
feature eliminates the need to periodically poll each connection to determine if any changes
in state have occurred. If the COS FIFO becomes full, background processes which monitor
for changes in connection state will be suspended until such time as the FIFO becomes able
to accept notifications of changes in state. Therefore, it is the responsibility of the
management software to ensure the COS FIFO is read often enough so that changes in state
remain compliant with the Bellcore and ITU standards.
If COS_EN is logic 0, the COS FIFO is disabled, and the background processes will not be
suspended. If COS_EN is logic 0, it is the responsibility of the management software to poll
each connection to determine changes in connection state (as reflected in the Status field of
the VC Table) and notify higher layers of any changes in state.
The updating of the COS FIFO can be enabled/disabled on a per-connection basis with the
COS_FIFO_enable bit of the Configuration field of the VC Table.
COS_Fail_Only
If the microprocessor has no need to know about changes of connection state unless they rise
to the level of a service failure (i.e. an OAM fault that persists for at least 4.5 +/- 0.5 seconds)
then, by setting this bit to logic 1, it may permit changes of state to be written to the COS
FIFO only when the OAM_Fail bit changes state. When this bit is set to logic 0, entries will
be made to the COS FIFO, on connections for which it is enabled, if any of the OAM alarms,
changes state. In any event, the COS_DRAM_ERR_EN controls whether DRAM CRC
errors cause COS entries.
COS_Fail_EN
When this bit is logic 1, changes on the OAM_Fail bit in the Status Field of a VC Table entry
will result in entries to the COS FIFO, so long as the COS FIFO is enabled both globally and
for that VC. When this bit is logic 0, changes in the OAM_Fail bit will not result in COS
FIFO entries.
Reserved
This bit should be programmed to logic 0.
COS_DRAM_ERR_EN
When this bit is logic 1, a CRC-10 error on the DRAM causes a Change of State entry to be
generated.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
194
PMC [ PMC-SIERRA, INC ]
