S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x043: SYSCLK DLL Register 4
Bit
31:8
7
6
5
4
3
2
1
Type
Function
Unused
Default
X
X
X
X
X
X
X
0
R
R
R
R
SYSCLKI
REFCLKI
ERRORI
CHANGEI
Unused
ERROR
CHANGE
RUN
R
R
R
0
0
The DLL Control Status Register provides information of the DLL operation.
RUN
The DLL lock status register bit RUN indicates the DLL has found a delay line tap in which
the phase difference between the rising edge of REFCLK and the rising edge of SYSLCK is
zero. After system reset, RUN is logic zero until the phase detector indicates an initial lock
condition. When the phase detector indicates lock, RUN is set to logic 1. The RUN register
bit is cleared only by a system reset or a software reset (writing to register 0x042).
CHANGE
The delay line tap change register bit CHANGE indicates the DLL has moved to a new delay
line tap. CHANGE is set high for eight SYSCLK cycles when the DLL moves to a new
delay line tap.
CHANGEI
The delay line tap change event register bit (CHANGEI) indicates the CHANGE register bit
has changed value. When the CHANGE register changes from a logic zero to a logic one, the
CHANGEI register bit is set to logic one. The CHANGEI register bit is cleared immediately
after it is read, thus acknowledging the event has been recorded.
REFCLKI
The reference clock event register bit REFCLKI provides a method to monitor activity on the
reference clock. When the REFCLK primary input changes from a logic zero to a logic one,
the REFCLKI register bit is set to logic one. The REFCLKI register bit is cleared
immediately after it is read, thus acknowledging the event has been recorded.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
187
PMC [ PMC-SIERRA, INC ]
