S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x042: SYSCLK DLL Register 3
Bit
31:8
7
6
5
4
3
2
1
Type
Function
Unused
TAP[7]
TAP[6]
TAP[5]
TAP[4]
TAP[3]
TAP[2]
TAP[1]
TAP[0]
Default
X
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
R
0
The DLL Delay Tap Status Register indicates the delay tap used by the DLL to generate the
outgoing clock. Writing to this register performs a software reset of the DLL.
TAP[7:0]
The tap status register bits TAP[7:0] specifies the delay line tap the DLL is using to generate
the outgoing clock DLLCLK. When TAP[7:0] is logic zero, the DLL is using the delay line
tap with minimum phase delay. When TAP[7:0] is all logic one, the DLL is using the delay
line tap with maximum phase delay. TAP[7:0] is invalid when vernier enable VERN_EN is
set to one.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
186
PMC [ PMC-SIERRA, INC ]
