S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x041: SYSCLK DLL Register 2
Bit
31:8
7
6
5
4
3
2
1
Type
Function
Unused
Default
X
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VERNIER[7]
VERNIER[6]
VERNIER[5]
VERNIER[4]
VERNIER[3]
VERNIER[2]
VERNIER[1]
VERNIER[0]
0
The Vernier Control Register provides the delay line tap control when using the vernier option.
VERNIER[7:0]
The vernier tap register bits VERNIER[7:0] specifies the phase delay through the DLL when
using the vernier feature. When VERN_EN is set high, the VERNIER[7:0] registers specify
the delay tap used. When VERN_EN is set low, the VERNIER[7:0] register is ignored. A
VERNIER[7:0] value of all zeros specifies the delay tap with the minimum delay through the
delay line. A VERNIER[7:0] value of all ones specifies the delay tap with the maximum
delay through the delay line.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
185
PMC [ PMC-SIERRA, INC ]
