RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
changes in the CAS values. Therefore, to avoid contention, the upper byte
should only be written when the idle detection is disabled.
Figure 25 Processor Controlled Configuration Register Structure
15
RX MASK
11
TX MASK
7
3
0
Reserved
Reserved
Once the processor determines that the status of a channel should change, the
processor should then write the TX Channel Active Table. The processor does
this by accessing the table 16 bits at a time. In most situations the processor will
want to change a subset of the 16 channels accessed. Therefore, a read-
modify-write will have to be performed.
Figure 26 shows the structure of the Active/Idle bit table. The index represents
the value that needs to be added to the base address of the table in order to
access the status for the channels located at that index.
Note that since the processor writes 16 bits at a time it is recommended that
processor intervention and automatic mode is not mixed within a group of 16
channels to avoid contention problems.
Figure 26 TX Channel Active/Idle Bit Table Structure
Index Line
Channel Status
0
1
2
0
0
1
15
31
15
14
30
14
13
29
13
12
28
12
11
27
11
10
26
10
9
25
9
8
24
8
7
23
7
6
22
6
5
21
5
4
20
4
3
19
3
2
18
2
1
17
1
0
16
0
13
14
15
6
7
7
31
15
31
30
14
30
29
13
29
28
12
28
27
11
27
26
10
26
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
25
24
23
22
21
20
19
18
17
16
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