RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
9.2.1.1.4 Idle Detection
Idle detection will be performed on a per queue basis using one of the following
three methods: channel associated signaling (CAS), out of band signaling
(processor controlled), or pattern matching. The status of each channel is stored
in the Active/Idle bit table. The mode for each channel is controlled by the value
of IDLE_CFG_n in the Idle Detection Configuration Table. The lower 16
channels or upper 16 channels of a line must not mix CAS or pattern matching
mode with processor controlled mode. This is to avoid contention updating the
active channel table.
9.2.1.1.4.1CAS Idle Detection
CAS idle detection looks at the ABCD bits in both the receive and transmit
direction and compares them to values programmed on a per channel basis by
the processor. If two consecutive CAS values match in both the receive and
transmit direction the channel is considered to be idle. The format of the register
(AUTO_CONFIG_n) in the CAS/Pattern Matching Configuration Table, which the
processor programs with the idle ABCD patterns, is pictured below in Figure 22.
The register also provides mask fields for the receive and transmit directions
which allow any one of the ABCD bits to be ignored when looking for a match.
Figure 22 CAS Idle Detection Configuration Register Structure
15
RX MASK
11
TX MASK
7
3
0
RX ABCD
TX ABCD
During CAS idle detection, a word is written to the Transmit Idle Interrupt FIFO
every time the status changes from active->idle or idle->active.
TIDLE_FIFO_EMPB is set as long as this FIFO contains any unread entries,
which will result in a maskable interrupt. The structure of the word contained in
the FIFO is shown in Figure 23. The upper eight bits indicate the channel that
encountered the status change and bit 0 indicates the status of the channel
(Active =1; Idle = 0). The processor accesses the FIFO by reading the
A1SP_TIDLE_FIFO register which will contain the top element of the FIFO.
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