RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 23 CAS Idle Detection Interrupt Word
8
1
15
13 12
8
7
2
0
Line
Channel
Unused
Status
9.2.1.1.4.2Processor Controlled Idle Detection
In Processor controlled idle detection mode, it is the responsibility of the
processor to add or drop channels. This mode is used in conjunction with
common channel signaling (CCS) or if the processor wants to make its own
determination of channel activity based on the CAS bits.
During the processor controlled idle detection, a word is written to the Transmit
Idle Interrupt FIFO every time the value of the CAS nibble changes and then
remains stable for one additional multiframe. TIDLE_FIFO_EMPB is set as long
as this FIFO contains any unread entries, which will result in a maskable
interrupt. The structure of the word contained in the FIFO is shown in Figure 24.
The first eight bits indicate the channel, which encountered a change in the value
of CAS. The next four bits indicate the RX CAS value and the final four bits
indicate the TX CAS value.
TX refers to the CAS incoming on the TDM interface (H-MVIP RL_SIG or direct
mode RL_SIG), and RX refers to CAS incoming in ATM cells at the UTOPIA Cell
Sink interface.
Based on these new CAS values the processor can make a determination if the
channel should be marked as active or idle. The CAS values are de-bounced
internally one time, and any additional debounce must be done external to the
chip.
Figure 24 Processor Controlled Idle Detection Interrupt Word
15
13 12
Line
8
7
4
3
0
Channel
RX CAS
TX CAS
The processor will also be able to mask out portions of the CAS and therefore
receive interrupts only when particular bits of the CAS change. Figure 25 shows
the structure of AUTO_CONFIG_n field in the CAS/Pattern Matching
Configuration Table. The lower byte is reserved and is used in detecting
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