RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
1) Once the TFTC writes a complete frame into external memory, it writes the
line number and frame number of this frame into the FR_ADVANCE_FIFO. The
CSD circuit reads the line-frame number pair from the FR_ADVANCE_FIFO and
uses it as an index into the Transmit Calendar. The Transmit Calendar is
composed of eight-bit tables, one per line. Each bit table consists of 128 entries,
one per frame buffer. Each entry consists of 32 bits, one per queue. For each bit
set in the indexed entry in the Transmit Calendar, the CSD will schedule the
frame in which the next cell can be built for the corresponding queue, and notify
the TALP that enough data is available to build a cell for that queue.
2) The CSD circuit processes all queues from the Transmit Calendar entry
starting with the lowest queue number and proceeding to the highest. The
processing steps are as follows:
a) The CSD circuit obtains the QUE_CREDITS, and subtracts the average
number of credits per cell from it. The average number of credits,
AVG_SUB_VALU, is the number of credits that will be spent sending the
current cell. For structured lines, the average number of credits per cell is 46
7/8. For unstructured lines, the average number of credits per cell is 47.
b) Next, the CSD circuit computes the frame location for the next service by
subtracting the remaining credits from 47. It divides the result by the number
of channels, NUM_CHAN, dedicated to that queue. The number of channels
is calculated based upon the Active/Idle bit table and the channels allocated
to the queue. If the chip is in non-DBCES mode, NUM_CHAN is equal to the
number of channels allocated to the queue. If the chip is in DBCES mode,
NUM_CHAN is equal to the number of allocated channels that are active,
which is determined from the Active/Idle table. The result is a frame
differential.
c) The CSD then adds this frame differential to the present frame location to
determine the frame number of the next frame in which the TALP can build a
cell. The CSD circuit then sets a bit in the corresponding entry in the Transmit
Calendar and writes to the QUEUE_CREDITS.
d) The CSD circuit then adds the new credits back to the credit total for the
frame increment number. The number of new credits is equal to the frame
differential computed earlier, multiplied by the number of channels for that
queue. Once a queue is identified as requiring service, its identity is written to
the NEXT_SERV location.
e) The CSD circuit obtains the next queue for that frame and repeats steps a.
through d. The CSD circuit continues this process until there are no more
active queues for that frame.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
90
PMC [ PMC-SIERRA, INC ]
