RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
mode this can be done by setting HS_TX_COND bit to a ‘1’. However a DS3 AIS
signal is a framed “1010” pattern. This signal can be generated by setting the
HS_GEN_DS3_AIS bit in the HS_LIN_REG register. The CMD_REG_ATTN bit
needs to be written to a ‘1’ after the HS_GEN_DS3_AIS bit or the HS_TX_COND
bit is set for this function to take affect.
9.2.1.1.2 Transmit Signaling Freezing
Signaling freezing is a required function when transporting CAS. This function
holds the signaling unchanged when the incoming line fails. The PMC-Sierra
framers provide this function. If a framer is used that does not support signaling
freezing, this function must be provided externally.
9.2.1.1.3 SRTS for the Transmit Side
The transmit side supports SRTS only for unstructured data formats on a per-line
basis. SRTS support requires an input reference clock, NCLK. The input
reference frequency is defined as 155.52/2n MHz, where n is chosen such that
the reference clock frequency is greater than the frequency being transmitted,
but less than twice the frequency being transmitted (2 x RL_CLK > NCLK >
RL_CLK). For T1 or E1 implementation, the input reference clock frequency
must be 2.43 MHz. The transmit side can accept a reference clock speed of up
to 77.76 MHz, which is required for DS3 applications. Figure 21 on page 84
shows the process implemented for each UDF line enabled for SRTS, regardless
of the reference frequency. One bit of resulting 4-bit SRTS code is then inserted
into the CSI bit of each of the odd numbered cells for that line. There are four
odd cells in each 8 cell sequence, so each one carries a different SRTS bit. If
the line does not supply SRTS, then all odd CSI bits are set to 0. The 3008
divider is the number of data bits in eight cells (8 x 8 x 47). The divider is aligned
on the first cell generation after a reset or a resynchronization to the cell
generation process.
Figure 21 Transmit Side SRTS Function
Server Clock Freque ncy
4-bit SRTS Code
RL_CLK
Latch
Divide By 3008
4-Bit Latch
4 Bits
Reset
Arm
Cell Generation
4 Bits
Input Reference Clock Frequency
N_CLK
Resync
(For T1/E 1, 2.43 MHz. For T3, 77 .76 MHz.)
4-Bit Counter
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
84
PMC [ PMC-SIERRA, INC ]
