RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Line 0
Line 0
ATTN0
DATA0
3
Line
Receive Line
Interface
Line Encoder
Interface
Line Number
•
•
•
ANY
•
•
•
4
16
Channel Pair
Line-to-Memory
Interface
Line 7
Line 7
ATTN7
DATA7
Line
Receive Line
Interface
16
Interface
16
Data
The receive line interface is primarily a serial-to-parallel converter. Serial data,
which is derived from the RL_DATA signal from the LI Block, is supplied to a shift
register. The shift register clock is the RL_CLK input from the external framer.
When the data has been properly shifted in, it is transferred to a 2-byte holding
register by an internally derived channel clock. This clock is derived from the line
clock and the framing information.
The channel clock also informs the line-to-memory interface that two data bytes
are available from the line. When the two bytes are available, a line attention
signal is sent to the line encoder block. However, because the channel clock is
an asynchronous input to the line-to-memory interface, it is passed through a
synchronizer before it is supplied to the line encoder. Since there are eight
potential lines and each of them provides its own channel clock, they are
synchronized before being submitted to the line encoder.
The TFTC accommodates the T1 Super Frame (SF) mode by treating it like the
Extended Super Frame (ESF) format. The TFTC ignores every other frame pulse
and captures signaling data only on the last frame of odd SF multiframes. The
formatting of data in the signaling buffers is highly dependent on the operating
mode. Refer to section 7.6.6 “RESERVED (Transmit Signaling Buffer)” on page
136 for more information on the transmit signaling buffer.
Figure 10 shows the format of the transmit data buffer for ESF-formatted T1 data
for lines that are in the SDF-MF mode.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
77
PMC [ PMC-SIERRA, INC ]
