RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 89 UI_SRC_INTF Start-of-Transfer Timing (Utopia 2 PHY Mode)
RPHY_CLK(i)
RPHY_ADDR(i)
RPHY_CLAV(o)
RPHY_ENB(i)
RPHY_SOC(o)
RPHY_PAR(o)
RPHY_DATA(o)
AAL1 Ad
AAL1_Ad
P1
D1
P2
D2
P3
D3
P
D
The end-of-transfer behavior is shown in Figure 90. As with Utopia 1 mode, the
state of RPHY_CLAV reflects the current cell transfer status and so remains
asserted until the last data byte/word. The SRC_INTF in this example does not
have another cell to send, so RPHY_CLAV shows a low value after the transfer.
Figure 90 UI_SRC_INTF End-of-Transfer Timing (Utopia 2 PHY Mode)
RPHY_CLK(i)
RPHY_ADDR(i)
RPHY_CLAV(o)
AAL1 Addr
RPHY_ENB(i)
RPHY_SOC(o)
RPHY_DATA(o) (16-bit)
RPHY_DATA(o) (8-bit)
D24
D50
D25
D51
D26
D52
D27
D53
Figure 91 is a functional timing of the SRC_INTF for the start of a cell transfer
when configured as an Any-PHY compliant receive slave. During a polling
operation, when the SRC_INTF determines that the UI_SRC_ADDR_CFG
address is on the bus it responds by driving RPHY_CLAV two cycles later. If
CS_MODE_EN is set in the UI_SRC_CFG register then CSB must also be
driven low one cycle after the RPHY_ADDR for proper response. If the
SRC_INTF has a cell to send it will drive RPHY_CLAV high and, as a result, the
master will activate RPHY_ENB to initiate a transfer. As with Utopia 2, the
SRC_INTF is selected if its address is on RPHY_ADDR inputs during the cycle
before RPHY_ENB goes low and in response transmits an entire cell.
RPHY_RSX is driven high during the prepended byte address and RPHY_SOC
is driven high during the first header byte of the ATM cell. Since data transfer
pausing is not supported, once a transfer is initiated, RPHY_ENB should remain
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
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PMC [ PMC-SIERRA, INC ]
