RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
13.2 Sink Utopia
In ATM master mode, the SNK_INTF block receives RATM_DATA, RATM_PAR,
RATM_SOC, and RATM_CLAV while driving RATM_ENB. During reset the
SNK_INTF tristates the RATM_ENB (and all other SRC_INTF outputs). After the
end of reset and after UI_EN in the UI_COMN_CFG register is set, if the
RATM_CLAV input signal is not asserted the SNK_INTF waits and RATM_ENB
is deasserted high. As shown in Figure 93, once the RATM_CLAV input signal is
asserted, the RATM_RENB output signal is asserted low 2 cycles later and it is
expected that the PHY slave will deliver the first data byte one cycle after RENB
goes low. Typically a start-of-cell signal will be sent by the PHY slave along with
the first byte of data, however RATM_SOC is optional and the RATM_SOC input
could be tied low. Note however, not using an SOC eliminates the possibility of
runt cell detection. Once RATM_ENB goes low, a counter is started, and 53
bytes are expected. If an SOC occurs within a cell, the counter reinitializes and
the previous corrupted cell will be dropped and the second good cell will be
received. The SNK_INTF block stores the ATM cell in the receive FIFO. The 4
cell MCFF FIFO allows the interface to accept data at the maximum rate and if
the FIFO fills, the RATM_ENB signal will not be asserted again until
RATM_CLAV is asserted and the device is ready to accept an entire cell. The
maximum supported clock rate is 52 MHz.
Figure 93 SNK_INTF Start-of-Transfer Timing (Utopia 1 ATM Mode)
RATM_CLK(i)
RATM_CLAV(i)
RATM_SOC(i)
RATM_DATA(i)
RATM_PRTY(i)
RATM_ENB(o)
D1
P1
D2
P2
D3
P3
D4
P4
D5
P5
D6
P6
Note that in ATM master mode the SNK_INTF uses cell based handshaking, thus
once a transfer has begun, RATM_ENB will be asserted continuously until the
end of the cell regardless of the state of RATM_CLAV. Figure 94 shows the end
of transfer signal behavior. In this example, since the PHY slave does not have
another cell to deliver, the RATM_CLAV signal is deasserted after the last byte is
delivered. Also, the AAL1GATOR acting as an ATM master always deasserts the
RATM_ENB at the end of a cell transfer. RATM_CLAV is then sampled again on
the following clock cycle, and if asserted, RATM_ENB will be asserted again for a
new transfer.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
312
PMC [ PMC-SIERRA, INC ]
