RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
is redefined as a RAM_R/WB and bursting is not used. A new address is
presented for each access along with the associated control (CSB, R/WB, OEB,
WEB). The write data is placed on the bus 2 cycles after the write address and
command The RAM_OEB is used to prevent bus contention when switching
from a write to a read. When switching from a read to a write, some bus
contention may be present but is minimal since the ZBTs SSRAMs are quick to
disable their buffers and the gator is slower to enable it’s buffers.
13.1 Source Utopia
In ATM master mode, the SRC_INTF block sources TATM_DATA, TATM_PAR,
TATM_SOC, and TATM_ENB while receiving TATM_CLAV. The Start-Of-Cell
(TATM_SOC) indication is generated coincident with the first word (8-bit or 16-
bit) of each cell that is transmitted on TATM_DATA. TATM_DATA, TATM_PAR,
and TATM_SOC are driven at all times. The write enable signal indicates which
clock cycles contain valid data for the Utopia bus. The device will not assert the
TATM_ENB signal until it has a full cell to send.
Note that during hardware/software reset, or when UI_EN in the UI_COMN_CFG
register is deasserted low, all Utopia interface outputs are tri-stated.
In ATM master mode, the SRC_INTF responds to the TATM_CLAV by beginning
a cell transfer as shown in Figure 85 below. If TATM_CLAV is asserted and the
UI_SRC_INTF has data to send, it will do so by asserting TATM_TENB while
driving data. Octet (byte) level handshaking and data transfer pausing is not
supported, thus although TPA_I may go low during the middle of a transfer as
shown in the Figure 85 example, the data transfer will still continue and TENB_O
will not be deasserted.
Figure 85 SRC_INTF Start of Transfer Timing (Utopia 1 ATM Mode)
TATM_CLK(i)
TATM_CLAV(i)
TATM_ENB(o)
TATM_SOC(o)
TATM_PAR(o)
TATM_DATA(o)
P1
D1
P2
D2
P3
D3
P4
D4
P5
D5
P6
D6
P7
D7
The end of a transfer for the SRC_INTF in Utopia 1 ATM Master mode is shown
in Figure 86. Per the Utopia 1 specification, TPA_I must be deasserted low by
the PHY slave at least four cycles before the end of the cell if the PHY cannot
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
307
PMC [ PMC-SIERRA, INC ]
