RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 94 SNK_INTF End-of-Transfer Timing (Utopia 1 ATM Mode)
RATM_CLK(i)
RATM_CLAV(i)
RATM_SOC(i)
RATM_DATA(i)
RATM_PAR(i)
RATM_ENB(o)
D50
P50
D51
P51
D52
P52
D53
P53
D1
P1
In PHY slave mode, the SNK_INTF block receives TPHY_DATA, TPHY_SOC,
and TPHY_ENB while driving TPHY_CLAV. TPHY_CLAV indicates when the
device is ready to receive a complete cell. In Utopia 1 mode, TPHY_CLAV is
always driven. In Utopia 2 mode, TPHY_CLAV is only driven during cycles
following ones in which TPHY_ADDR[4:0] matches the address CFG_ADDR[4:0]
in the UI_SNK_ADDR_CFG register.
Figure 95 below shows the start of transfer timing for Utopia 1 Phy slave mode.
At reset, and when UI_EN in the UI_COMN_CFG register is set low, the
SNK_INTF block tristates TPHY_CLAV (not shown). While not in reset, the
SNK_INTF asserts TPHY_CLAV if it can accept a cell and waits for TPHY_ENB
to be asserted.
When TPHY_ENB is asserted, a counter is started and 53 bytes are received (27
words in 16-bit mode). If a new TPHY_SOC occurs within a cell, the counter
reinitializes. This means that the corrupted cell will be dropped and the second
good cell will be received.
In Utopia 1 PHY mode, the SNK_INTF will accept data as long as TPHY_ENB is
asserted and the sink MCFF FIFO has room. Data transfer pausing is supported
in Utopia 1 PHY mode, thus if TPHY_ENB is deasserted, as in Figure 95, the
data transfer is paused. The 8 cell MCFF FIFO allows the interface to accept
data at the maximum rate. If the FIFO fills, the TPHY_CLAV signal will be
deasserted by data transfer cycle D12 (D10 in 16-bit mode) and not be asserted
again until the device is ready to accept an entire cell (This is not shown in a
figure).
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
313
PMC [ PMC-SIERRA, INC ]
