RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
13
FUNCTIONAL TIMING
This section shows the functional relationship between inputs and outputs. No
propagation delays are shown.
Figure 83 Pipelined Single-Cycle Deselect SSRAM
REF_CLK
RAM_CSB
RAM_ADSCB
RAM_OEB
RAM_A(17:0)
RAM_D(31:0)
RAM_WE0B
RAM_WE1B
ADDR0
ADDR 1
ADDR2
RD DATA0
WRT DATA1
READ DATA2
The diagram above illustrates the SSRAM accesses when it is configured to use
a pipelined single-cycle deselect SSRAM. In this mode, ADSC is used and
bursting is not used. A new address is presented for each access along with the
associated control (CSB, ADSCB, OEB, WEB). The RAM_ADSCB signal is
pulsed during the last cycle of a read prior to a write to place the SSRAM into a
deselect state. The deselect state of the SSRAM causes the SSRAM to tristate
it’s data bus after the rising edge of the clock. This operation reduces contention
on the bus when switching from a read to a write operation. The RAM_OEB is
used to prevent bus contention when switching from a write to a read.
Figure 84 Pipelined ZBT SSRAM
REF_CLK
RAM_CSB
RAM_OEB
RAM_A(17:0)
ADDR0
ADDR 1
ADDR2
RAM_D(31:0)
RAM_ADSC/RAM_R/WB
RAM_WE1B
RD DATA0
WRT DATA1
RD DATA2
RAM_WE0B1
The diagram above illustrates the SRAM accesses when it is configured to use
the pipelined ZBT SSRAM for improved throughput. In this mode, RAM_ADSC
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
306
PMC [ PMC-SIERRA, INC ]
