RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 61 Direct Adaptive Clock Operation
Line Interface
with Transmit
Jitter Attenuator
TL_DATA
Framer
TL_SIG
TL_CLK
Frame
Difference
AAL1 SAR Processor
Gain
(AAL1gator 8/4)
Frequency
Synthesizer
Use Nominal
Frequency
Nominal Frame Difference
Channel Status
Underrun
9.3.3.8 Frequency Synthesizer
The Frequency Synthesizer block receives an 8-bit two’s complement number to
select a frequency setting. Although possible (with 8 bits) to input a value of –
128 to 127 this input is limited internally to –83 to 88 for T1 and –128 to 111 for
E1. This is done in order to not exceed the frequency range specification of +/-
200ppm for T1 and +/- 100ppm for E1. Based on this value, the Frequency
Synthesizer synthesizes a clock for each line. The line frequency is synthesized
by dividing down the 38.88 MHz system clock. The method for dividing down the
system clock is dependent on whether the line is in T1 or E1 mode.
In order for this block to work properly, the system clock must be 38.88 MHz. The
accuracy of the synthesized clock is dependent on the accuracy of SYS_CLK.
Therefore, if a 50 ppm T1 clock is desired, SYS_CLK needs to be a 38.88 MHz
clock signal with 50 ppm accuracy. To lock the synthesized clock to a network
clock, be sure SYS_CLK is derived from the network clock. This block can be
accessed through the CGC serial data in port, and it is also used internally by the
SRTS and adaptive algorithms
To minimize jitter, long and short cycles are distributed. The resultant
synthesized clocks meet G.823 and G.824 specs for jitter. Jitter can be further
reduced by running the TL_CLKs through a jitter attenuator in the framer or LIU.
The synthesizers can be set to operate in normal or high resolution mode. In
normal mode only the 4 high order bits of the frequency setting value are
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