RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Table 7 Buffer Depth
CGC_LINE_OUT[4:0]
Value
CGC_DOUT[3:0] Value
3
2
1
0
5
4
3
2
1
0
queue(7)
queue(3)
queue(6)
queue(2)
queue(5)
queue(1)
queue(4)
queue(0)
0
0
buff_depth(13)
buff_depth(9)
buff_depth(5)
buff_depth(1)
buff_depth(12)
buff_depth(8)
buff_depth(4)
buff_depth(0)
Buff_depth(11)
Buff_depth(7)
Buff_depth(3)
buff_depth(10)
buff_depth(6)
buff_depth(2)
Figure 58 Adaptive Data Functional Timing
SYSCLK
CGC_DOUT(3:0)
CGC_LINE(4:0)
SRTS_STB
A
5
0
4
8
3
0
2
2
1
B
0
ADAP_STB
9.3.3.5 Ext Freq Select Interface
The Ext Freq Select Interface allows an external source to directly select the line
clock frequency from any one of 171 T1 or 240 E1 frequencies centered around
the nominal clock rate. For T1 the legal input values are –83 to 88. For E1 the
legal input values are –128 to 111. Any values outside of this range will be
clamped to these levels. These levels correspond to a +/-200 ppm T1 clock and
a +/- 100 ppm E1 clock. See section 9.3.3.8 for more detailed information.
The External Interface block has two input ports that allow an external source to
control the frequency synthesizers internal to the CGC. These two ports are
CGC_SER_D and CGC_VALID. CGC_SER_D contains the data that selects
one of the 171/240 frequencies and CGC_VALID indicates when this data is
valid. There should be a rising edge of CGC_VALID at the start of each timing
message. And CGC_VALID should go low at the end of each timing message.
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