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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
the amount of weighting is programmable. The following formula is used to  
determine the average buffer depth.  
(PrevAvgDepth * (N-1)) + CurBufDepth  
N
N = Weighting = 2^Adap_Filt_Size  
PrevAvgDepth = Previous Average Buffer Depth  
CurBufDepth = Current Buffer Depth  
N must be a power of 2 and is controlled by the ADAP_FILT_SIZE field in the  
A_ADAP_CFG register. If ADAP_FILT_SIZE equals ‘0’ then no filtering is done.  
To enable quicker lock times, the window size will start small and will grow until it  
matches the ADAP_FILT_SIZE parameter. The average value will reset when  
either the line is disabled or it goes into underrun.  
The value sent to the synthesizers is a truncated value of the Relative Buffer  
Depth. Relative Buffer Depth is the difference between the calculated average  
buffer depth and the CDVT setting (R_CDVT in the receive queue table) which  
represents the ideal buffer depth value. The Relative Buffer Depth is limited to  
represent a value of +/- 8 frames (ie, +/- 256 bytes) from the CDVT setting.  
Relative buffer depths that exceed this value are truncated to a max/min value of  
+/- 8 frames. Using a signed 8 bit data value, this corresponds to 1 bit  
representing 2 bytes of data.  
The frequency synthesizer will further cap this value by limiting the frequency  
range to +/- 200 ppm for T1 and +/-100 ppm for E1.  
Note that adaptive clocking, in general, is not well suited for voice applications  
since low frequency or DC changes of the CDV will pass through most filters and  
cause frame slips. Adaptive clocking is only supported for unstructured  
connections inside the AAL1gator. If adaptive clocking is desired for structured  
connections, it will need to be processed externally. The buffer depth will be  
played out for each queue, but the information will be in frames. (the bottom 5  
bits are invalid).  
If an alternative algorithm is desired, this can be handled externally following an  
architecture similar to what is shown in Figure 61. Note that the internal  
synthesizers can be used via the CGC control port, so that only the adaptive  
algorithm has to be in external logic and not the synthesizers.  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
146  
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