RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
CGC_VALID only needs to be deactivated for one cycle between timing
messages. The CGC block decodes the incoming line number, and if the
address matches one of its 32 line numbers, passes the data on to the
appropriate frequency synthesizer.
Figure 59 below shows an example of where Line 19 is being programmed to run
with the frequency setting of –79 (Two’s complement). See the section on the
Frequency Synthesizer block for a discussion of the different frequency settings
which range from -83 to 88 in T1 mode and –128 to 111 in E1 mode.
Figure 59 Ext Freq Select Functional Timing
Line Number
Frequency Setting
SYSCLK
CGC_SER_IN
CGC_SER_VAL
9.3.3.6 SRTS
SRTS functionality is enabled by setting the SRTS_EN bit in the
LIN_STR_MODE memory register. To disable SRTS processing on the chip via
hardware, tie the NCLK/SRTS_DISB signal to ground.
When enabled, the local SRTS values, which are calculated within this SRTS
block, are subtracted from the SRTS values received in the cells received by
RALP, which represent the remote SRTS values. This SRTS difference is sent
by the SRTS block to the Frequency Synthesizer to indicate what frequencies
should be synthesized for each line. The SRTS difference is also played out
externally.
SRTS is supported for unstructured data formats on a per-line basis. SRTS
support requires an input reference clock (NCLK). The input reference frequency
is defined as 155.52 / 2n MHz, where n is chosen so the reference clock
frequency is greater than the frequency being transmitted, but less than twice the
frequency being transmitted (2 x TL_CLK > NCLK > TL_CLK). For T1 or E1
implementations, the input reference clock frequency is 2.43 MHz and must be
synchronized to the ATM network. Figure 60 shows the process implemented for
each UDF line enabled for SRTS. The CGC generates a local SRTS value from
the network clock (NCLK) and the local TL_CLK. It makes a request to the A1SP
to read a new remote SRTS value from the SRTS queue and, at the appropriate
time, generates a 4-bit two’s complement code that indicates the difference
between the locally generated SRTS value and the incoming SRTS value. The
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