RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
1. external playout of Adaptive, SRTS, and Channel Status data
2. receipt of external frequency select data.
The External Interface block transmits either SRTS, Adaptive, or Channel Status
information on a line basis which enables an external decision to made about
altering the line clock frequency. The SRTS output data is the difference
between the local and remote SRTS nibble. The adaptive output data is the
averaged (using the adaptive algorithm described in section 9.3.3.7) relative
buffer depth in units of bytes. If the adaptive weighting is set to 0 this value
becomes the raw buffer depth in units of bytes.
Status information is played out on the External Clock Generation Control (CGC)
Interface which includes the external output signals: CGC_DOUT[3:0],
CGC_LINE[4:0], SRTS_STBH, and ADAP_STBH.
Information is played out for all chip modes (Direct, H-MVIP).
The interface clocking operates according to the following pseudocode:
• If a channel pair is being serviced, start a state machine to play out the
channel status, as shown in Table 6, asserting ADAP_STBH as each state is
played out.
• Else, if an SRTS difference value is ready, it is played out with SRTS_STBH
asserted and ADAP_STBH deasserted.
• Else if a cell is received and a valid averaged relative buffer depth can be
computed, start a state machine to play out the averaged relative buffer depth
and queue number, as shown in Table 7, asserting ADAP_STBH as each
state is played out.
• Once playout of a certain data type has begun it will not be interrupted.
9.3.3.2 SRTS Data Output
In SRTS mode the CGC block puts out a 4 bit value which represents the
difference between the local SRTS value and the received SRTS value. Figure
56 below shows a typical CGC output in SRTS mode.
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PMC [ PMC-SIERRA, INC ]
