RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
The CGC consists of four major blocks: External Interface, SRTS, Adaptive, and
Frequency Synthesizer. The External Interface passes SRTS and adaptive
information out to the user and allows the user to control the Frequency
Synthesizer. The SRTS block receives SRTS values and uses the values to
determine the frequency to be synthesized. The Adaptive block receives buffer
depth information and uses this information to determine the frequency to be
synthesized. The Frequency Synthesizer block synthesizes any one of 256
possible frequencies centered around either the T1 or E1 nominal frequency
based upon an 8-bit select value. The synthesized frequency is derived from the
38.88 MHz system clock.
The transmit line clock source is controlled by the CLK_SOURCE_TX field and
the T1_MODE bit in the LIN_STR_MODE memory register. The eight possible
options are:
000
001
010
Use external clock. (TL_CLK is an input).
LOOPED – Use RL_CLK as the clock source.
NOMINAL Synthesized – Generate a clock of the nominal (T1
or E1) frequency from SYS_CLK.
011
100
101
SRTS Synthesized- Generate a clock frequency based on the
received SRTS values.
ADAPTIVE Synthesized- uses receive buffer depth to control
TL_CLK
Externally controlled Synthesized: Generate a clock frequency
based on the values provided by CGC_SER_D pin. This mode
is used for external implementations of SRTS or Adaptive
clocking.
110
111
Use common external clock (CTL_CLK) (Not valid in H-MVIP
mode)
If in Direct Low Speed Mode, use common external clock
(CTL_CLK) and drive TL_SIG data onto TL_CLK pin. Not valid
in other modes.
Options “010” through “101” involve the CGC block. Each line is independently
controlled. When a particular line is not in one of these modes it is held in reset.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
138
PMC [ PMC-SIERRA, INC ]
