RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
correctly so the time delay value of the SRTS data matches the time delay value
of the signal data. The RFTC queues the SRTS nibbles and then fetches when
requested by the AAL1 Clock Generation Control block. If the SRTS queue
overruns or underruns, the value is indicated as invalid.
Note SRTS can be used with the internal clock synthesizers for E1 and T1 mode.
If other frequencies are used including DS3 and E3, an external clock
synthesizer needs to be used.
Figure 55 Receive Side SRTS Support
Function Inside of RALP
R_SRTS_CDVT
Difference between
Remote SRTS and
Local SRTS
Cell Reception
SRTS Bit
Remote SRTS
SRTS
Queue
Extraction
Line Clock
Frequency
Latch
Divide by 3008
4-Bit Latch
Local SRTS
4-Bit Count
Input Reference Clock Frequency
NCLK (For T1/E1 = 2.43 MHz; For T3
= 77.76 MHz
4-Bit Counter
9.3 AAL1 Clock Generation Control
9.3.1 Description
The CGC block is responsible for generating the A1SP transmit line clocks. A
given line clock is synthesized internally using a 38.88 MHz system clock
(SYS_CLK). Only E1 or T1 clocks can be generated internally. Any other
frequency clock must be generated externally and passed into the AAL1gator-8
as an input. The frequency of the synthesized clock can be controlled via an
external input, the internal SRTS algorithm, or the internal adaptive algorithm.
Alternatively a nominal E1 or T1 frequency clock can be generated. Each line
clock can be controlled independently. To assist an external source in
determining what frequency to use, SRTS and adaptive information is output
using the external interface. The CGC block also outputs status information for
channel pairs through the external interface.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
137
PMC [ PMC-SIERRA, INC ]
