PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
The adaptive clocking mechanism shares the SRTS port with the SRTS mechanism. It operates
according to the following psuedocode:
If an SRTS difference value is ready, it is played out with SRTS_STRB asserted and
ADAP_STRB deasserted. The SRTS values have higher priority than the adaptive clock
values.
Else if a channel pair is being serviced, start a state machine to play out the channel status,
as shown in Table 3 on page 72, asserting ADAP_STRB as each state is played out.
Else if a cell is received and a valid frame difference can be computed, start a state
machine to play out the frame difference and queue number, as shown in Table 4 on
page 72, asserting ADAP_STRB as each state is played out.
The playout of the channel status may interrupt the playout of the frame difference at any point.
Table 3. Channel Status
SRTS_DOUT(3:0) Value
SRTS_LINE(3:0)
Value
3
2
1
0
15
14
13
0
line(2)
line(1)
line(0)
channel(4)
underrun_h
channel(3)
resume_h
channel(2)
underrun_1
channel(1)
resume_1
NOTES:
•
The underrun bit goes high when underrun occurs and will stay high until the underrun
condition is cleared.
•
Resume goes high when the underrun condition is cleared and goes low when the read
pointer equals the underrun_end pointer.
•
•
The status is played out once for every 16 receive line clocks.
The channel values (4:1) identify 16 channel pairs. The odd and even numbered channels of
each pair are carried by the high and low bits, respectively.
•
For UDF-ML mode, the values in channel (4:1) and underrun_l can be ignored. Line (2:0)
indicate the line number and underrun_h represents the queue status.
Table 4. Frame Difference
SRTS_DOUT(3:0) Value
SRTS_LINE(3:0)
Value
3
2
1
0
5
4
cell_vci(7)
cell_vci(3)
cell_vci(6)
cell_vci(2)
cell_vci(5)
cell_vci(1)
cell_vci(4)
cell_vci(0)
ꢆꢁ
PMC [ PMC-SIERRA, INC ]
