PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
which requires an external Voltage Controlled Crystal Oscillator (VCXO) to generate the clock.
Refer to section 8.7 “UDF-HS Mode SRTS-Based Clock Recovery Application for DS3” on page
180 for an application note on high speed SRTS.
The E1 SRTS synthesizer can generate an E1 clock over a ± 90 ppm range, while the T1 SRTS
synthesizer can generate a T1 clock over a ± 200 ppm range to accommodate older T1 equipment.
Due to the T1 synthesizer’s wider range, it has a more jitter than the E1 synthesizer. While the E1
synthesizer falls well within the G.823 jitter mask, the T1 synthesizer has a spike at 8 kHz that
exceeds the mask. However, in both cases using an LIU with a built-in jitter attenuator, such as
®
the Level One LXT305A, eliminates most of the jitter and is recommended when using SRTS.
Refer to section 8.10.3 “SRTS T1 Clock” on page 188 and section 8.10.4 “SRTS E1 Clock” on
page 191 for the jitter characteristics of the SRTS synthesizer both with and without the external
jitter attenuator.
R_SRTS_CDVT
Cell Reception
SRTS Bit
Extraction
Remote 4-Bit
SRTS-Code FIFO
SRTS
Queue
Difference Between
Remote SRTS Code and
Local SRTS Code.
Server Clock Frequency
TL_CLK
4 Bits
Latch
Divide By 3008
4-Bit Latch
Local 4-Bit SRTS Code
4 Bits
Input Reference Clock Frequency
N_CLK
(For T1/E1, 2.43 MHz. For T3, 77.76 MHz.)
4-Bit Counter
Figure 51. Receive Side SRTS Support
3.7.2 Adaptive Clock Operation
The adaptive clock provides a queue depth difference for control of an external clock. If the depth
is low, then the clock frequency should be reduced. If the depth is high, then the clock frequency
should be increased. If no data is received, the channel status specifies to either freeze the external
clock or to set it to a nominal rate.
The AAL1gator II supports adaptive clocking in SDF-FR, SDF-MF, and UDF-ML modes. It sup-
ports adaptive clocking for all connection types within these three modes, including those with
partially filled cells or only a single DS0. The device does not support adaptive clocking in
UDF-HS mode.
ꢆꢀ
PMC [ PMC-SIERRA, INC ]
