PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
The AAL1gator II will generate the TL_CLK based on the value of CLK_SOURCE bits in LIN_
STR_MODE (refer to section 7.4.3 “LIN_STR_MODE” on page 126). Once the LIN_STR_
MODE and line mode information is read, the TL_CLK switches to the desired clock. The four
clock choices are: looped RL_CLK, synthesized nominal E1 or T1 clock, a synthesized clock
based on the SRTS received values, or an externally generated clock.
For the period of time after the AAL1gator II receives a hardware reset and before the LIN_STR_
MODE is read, the TL_CLK operation is dependent on TLCLK_OUTPUT_EN. If the TLCLK_
OUTPUT_EN input is tied low, then the TL_CLK pins are inputs and the clock is externally gen-
erated. And if TLCK_OUTPUT_EN is high, then TL_CLK defaults to the looped RL_CLK.
NOTES: • The TLCLK_OUTPUT_EN input controls all lines. Therefore TL_CLK will be
generated for all lines or for no lines upon power up. Once the LIN_STR_MODE
information is read, each individual TL_CLK may be generated differently
according to the CLK_SOURCE bits for that queue. There will be a discontinuity
in the clock when switching from one source to another.
• If a synthesized clock is selected but SW_RESET (refer to “SW_RESET” on
page 165) is set, the output clock will be “0”. To maintain a continuous clock,
define the CLK_SOURCE bits equal to the default value the first time the CMD_
REG_ATTN bit is written (SW_RESET = “1”). Then when clearing SW_RESET,
set the CLK_SOURCE bits to the desired value and set the CMD_REG_ATTN
bit again. This will read the old configuration values, but with the new CLK_
SOURCE values.
3.7.1.1 Recovered Mode
Set the CLK_SOURCE bits in the LIN_STR_MODE register for that line to “01”, to generate a
clock based on the received RL_CLK. This will put the line into recovered mode. This change
will not take affect until the CMD_REG_ATTN bit is set.
3.7.1.2 Synthesize a Nominal E1 or T1 Clock
To generate a nominal E1 or T1 clock, set the CLK_SOURCE bits in the LIN_STR_MODE reg-
ister for that line to “10”. This change will not take affect until the CMD_REG_ATTN bit is set.
The AAL1gator II can synthesize a nominal E1 clock or T1 clock that is derived from SYS_CLK.
For this mode, SYS_CLK must be 38.88 MHz. The accuracy of the synthesized clock is depen-
dent on the accuracy of SYS_CLK. Therefore, if a 50 ppm T1 clock is desired, SYS_CLK needs
to be a 38.88 MHz clock signal with 50 ppm accuracy. To lock the synthesized clock to a network
clock, be sure SYS_CLK is derived from the network clock.
ꢅꢈ
PMC [ PMC-SIERRA, INC ]
