PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
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AAL1 SAR Processor
Adaptive clocking, in general, is not well-suited for voice applications since low frequency or DC
changes of the CDV will pass through most filters and cause frame slips. The mechanism shown
in Figure 52 can be enhanced for voice applications by adding a low pass filter with a time con-
stant greater than the CDV, along with a fine-granularity frequency synthesizer.
Line Interface
TL_SER
with Transmit
Jitter Attenuator
Framer
TL_SIG
TL_CLK
Frame
Difference
AAL1 SAR Processor
(AAL1gator II)
Gain
Frequency
Synthesizer
Use Nominal
Frequency
Nominal Frame Difference
Channel Status
Underrun
Figure 52. Direct Adaptive Clock Operation
3.8 Memory Interface and Arbitration Controller (MIAC)
The MIAC is the central arbiter for all memory accesses. It provides a priority mechanism that
incorporates fairness to satisfy all real-time requirements of the various blocks. All blocks
requesting a data transfer with the common memory supply the address, control signals, and the
data, if the requested data transfer is a write, to the MIAC. When the MIAC actually grants the
transfer, it provides a grant signal to the requesting block, indicating that the transfer has been
performed. The memory is arbitrated on a cycle-by-cycle basis. No device is granted the bus for
an indefinite time.
The AAL1gator II requires external memory address buffers and data transceivers. The MIAC
provides control signals and transceiver enables when a microprocessor cycle is to be performed.
The device can directly control external 646-type registered transceivers on the data bus between
the memory data interface and the microprocessor’s data bus. The SP_DATA_CLK signal con-
trols the writing of data from the memory into the 646 transceiver. The SP_DATA_DIR signal
and SP_DATA_EN signal should be used to direct the data through the 646s devices properly.
The /SP_ADD_EN signal should be used as a tristate enable for the external address buffers. The
AAL1gator II controls the tristating of its own address and data bus drivers so no conflicts occur
with the microprocessor external buffers.
ꢆꢃ
PMC [ PMC-SIERRA, INC ]
