PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Refer to section 8.10.1 “Nominal T1 Clock” on page 185 and section 8.10.2 “Nominal E1 Clock”
on page 187 for jitter characteristics of a synthesized clock. It is recommended that a Line Inter-
face Unit (LIU) with a built in jitter attenuator, such as the Level One LXT305A, be used to
obtain improved jitter characteristics.
3.7.1.3 Synthesize an E1 or T1 Clock based on SRTS
NOTE: The AAL1gator II uses Bellcore’s patented SRTS clock recovery technique. Refer to
the NOTE on page 172 for additional information regarding Bellcore’s SRTS patent.
Set the CLK_SOURCE bits in the LIN_STR_MODE register for that line to “11” to generate an
E1 clock or T1 clock based on received SRTS values. This change will not take affect until the
CMD_REG_ATTN bit is set.
For this mode, SYS_CLK must be 38.88 MHz. For SRTS, it is recommended that SYS_CLK has
an accuracy of ± 100 ppm. Since a network derived N_CLK is used, SYS_CLK does not have to
be derived from the network clock.
The AAL1gator II supports SRTS for unstructured data formats on a per-line basis. SRTS support
requires an input reference clock (N_CLK). The input reference frequency is defined as 155.52 ÷
2^n MHz, where n is chosen so the reference clock frequency is greater than the frequency being
transmitted, but less than twice the frequency being transmitted (2 × TL_CLK > N_CLK > TL_
CLK). For T1 or E1 implementations, the input reference clock frequency is 2.43 MHz and must
be synchronized to the ATM network. Figure 51 on page 71 shows the process implemented for
each UDF line enabled for SRTS. The RFTC also generates a local SRTS value from the network
clock (N_CLK) and the local TL_CLK. It queues the incoming SRTS values, and, at the appropri-
ate time, generates a 4-bit two’s complement code that indicates the difference between the
locally generated SRTS value and the incoming SRTS value. The value of this code ranges from
-8 (1000) to +7 (0111). A higher value than had been output previously indicates the remote clock
is running faster than the local clock. A lower value than had been output previously indicates the
remote clock is running slower than the local clock. The RFTC uses this value internally to syn-
thesize the TL_CLK.
The RFTC supports SRTS only for unstructured data formats on a per-line basis. The SRTS_
CDVT value in R_SRTS_CONFIG register must be configured correctly so the time delay value
of the SRTS data matches the time delay value of the signal data. The RFTC queues the SRTS
nibbles and then fetches it before it is needed. If the SRTS queue overruns or underruns, a value
of 0000 is used.
The RFTC also outputs the SRTS difference through a multiplexed interface. This value can be
used by external logic to synthesize the TL_CLK. Refer to section 6.7 “SRTS Timing” on page
118 for timing of this interface. This interface is needed for high speed mode (E3 or DS3) SRTS
ꢆꢉ
PMC [ PMC-SIERRA, INC ]
