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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
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AAL1 SAR Processor  
uses the synchronization signals (TL_FSYNC and TL_MSYNC) supplied by the framer to per-  
form a parallel-to-serial conversion on the outgoing data that it reads from a multiframe buffer in  
the order in which it is needed.  
A rising edge on TL_FSYNC indicates the beginning of a frame, and a rising edge on TL_  
MSYNC indicates the beginning of a multiframe. The RFTC realigns when an edge is seen on  
these signals. It is not necessary to provide an edge every frame or multiframe. Signaling data is  
driven for all frames of any multiframe and will change only on multiframe boundaries. For T1  
mode, signaling data may change every 24th frame. For E1 mode, signaling may change every  
16th frame.  
A special case of E1 mode exists that permits the use of T1 signaling with E1 framing. Normally  
an E1 multiframe consists of 16 frames of 32 timeslots, where signaling changes on multiframe  
boundaries. When E1_WITH_T1_SIG is set in LIN_STR_MODE and the line is in E1 mode, the  
TFTC will use a multiframe consisting of 24 frames in 32 timeslots. In this mode, the  
AAL1gator II reads signaling on the 24th frame of the multiframe.  
The signaling nibble is valid for each channel when the last nibble of each channel’s data is being  
driven. See Figure 48 for an example of signaling bits in a T1 frame. See Figure 49 for an exam-  
ple of signaling bits in the E1 mode.  
Line Output Signals During Every Frame  
21  
TL_SER  
(timeslots)  
0
1
2
22  
ABCD  
23  
ABCD  
XXXX  
Channel 23  
...  
ABCD  
ABCD  
XXXX  
ABCD  
ABCD  
XXXX Channel 21  
TL_SIG XXXX  
XXXX  
...  
XXXX  
...  
Channel 1  
Channel 2  
Channel 22  
Channel 0  
XXXX - indicates signaling is invalid  
Figure 48. Output of T1 Signaling Bits  
Line Output Signals During Every Frame  
TL_SER  
(timeslots)  
0
1
2
29  
30  
ABCD  
31  
ABCD  
XXXX  
Channel 31  
...  
ABCD  
ABCD  
XXXX  
ABCD  
ABCD  
XXXX Channel 29  
XXXX  
TL_SIG XXXX  
...  
XXXX  
...  
Channel 1  
Channel 2  
Channel 30  
Channel 0  
XXXX - indicates signaling is invalid  
Figure 49. Output of E1 Signaling Bits  
NOTE: The AAL1gator II treats all 32 timeslots identically. Although E1 data streams con-  
tain 30 timeslots of channel data and 2 timeslots of control (timeslots 0 and 16), data  
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