PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
3.6.5 Counters and Sticky Bits
The RALP sets sticky bits for overrun, underrun, pointer mismatch, resume, SRTS underrun,
SRTS resume, and other conditions. As with all registers, the sticky bits are located in the external
RAM. They are set by the AAL1gator II and must be cleared by the microprocessor. Sticky bits
provide a history of events that have occurred. Since these bits can be set with every cell, it is bet-
ter to use the counters for statistics gathering purposes. The AAL1gator II increments the counters
for incorrect SNs, incorrect SNPs, cells received, underflows, overflows, dropped cells, misin-
serted cells, lost cells, pointer parity errors, and pointer mismatches. The transfer status bits can
be used to detect that a clear was overwritten by toggling transfer bit 15 with each clear of the sta-
tus bits and then reading the value immediately thereafter. Refer to “R_ERROR_STKY Word
Format” on page 158 for a description of sticky bits.
3.6.6 OAM Cells
When an OAM cell arrives, the RALP stores it in the OAM queue. The RALP notifies the micro-
processor of the arrival of OAM cells by generating an interrupt. The interrupt is cleared when the
CLR_RX_OAM_LATCH (refer to “CMDREG Word Format” on page 165) is set. The micro-
processor reads the OAM cells from the OAM queue. The microprocessor maintains the OAM_
HEAD value. The RALP maintains the OAM_TAIL value. The AAL1gator II also checks the
CRC-10 of the cell and records the results in the receive buffer in the CRC_10_PASS parameter
(refer to “R_OAM_CELL_n Format” on page 163).
3.6.7 Interrupt Handling
The AAL1gator II uses the following algorithm to handle interrupts:
1. An internal register called the command register (refer to section 7.9 “CMDREG (Command
Register)” on page 165) handles interrupts. This command register has an OAM_INT_MASK
bit. The microprocessor can access the command register by asserting the ADDR17 pin, the
/PROC_CS signal, and either the /PROC_RD or the /PROC_WR signal.
2. At the end of an OAM cell, the RALP generates an interrupt to the microprocessor. If the
mask bit is set, the RALP does not present the interrupt to the interrupt pin.
3. At the end of any cell (either an OAM or data cell), the head and tail pointers of the OAM
queue table are compared. If they do not match (that is, if there are cells in the OAM FIFO),
the RALP sets the interrupt latch.
3.7 Receive Frame Transfer Controller (RFTC)
The RFTC moves data bytes from the receive frame buffer to the appropriate timeslot of the
appropriate line. It must perform a timeslot-to-queue translation for each timeslot by reading the
receive channel-to-queue table (refer to section 7.8.6 “R_CH_TO_QUEUE_TBL” on page 148).
The RFTC outputs data to the external T1 or E1 framer device. For structured data, the RFTC
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PMC [ PMC-SIERRA, INC ]
